1

[Accepted. Nov. 2022]
S. Lee, Y. Lee, G. Kim, T. Eom, S.-O. Jung, and S. Jeon, “Effect of floating gate insertion on the analog states of ferroelectric field-effect transistors," IEEE Transactions on Electron Devices

2

[Accepted. Nov. 2022]
S. Lim, D. H. Ko, S. k. Kim, and S.-O. Jung, “Cross-coupled Ferroelectric FET-based Ternary Content Addressable Memory with Energy-Efficient Match Line Scheme," IEEE Transactions on Circuits and Systems I: Regular Papers

3

[Accepted. Sep. 2022]
T. W. Oh, J. Park, T. Kim, K. Cho, and S.-O. Jung, “Local Bit-Line SRAM Architecture with Data-Aware Power-Gating Write Assist," IEEE Transactions on Circuits and Systems II: Express Briefs

4

[Jun. 2022]
J. Hwang, S. Lim, G. Kim, S. Jeon, and S.-O. Jung, “A Non-Volatile Majority Function Logic Using Ferroelectric Memory for Logic in Memory Technology," IEEE Electron Device Letters, Vol.43, Issue. 7, Pages 1049-1052

5

[Jun. 2022]
J. Y. Kim, J. S. Lee, K. Kim, S. Joo, B. M. Moon, K. Sohn, and S.-O. Jung, “A 5Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3D-Stacked IC," IEEE Journal of Solid-State Circuits, Vol.57, Issue. 6, Pages 1913-1926

6

[Apr. 2022]
K. Cho, H. Choi, I.-J. Jung, J. Oh, T. W. Oh, K. Kim, G, Kim, T. Choi, C. Sim, T. Song, and S.-O. Jung, “SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling," IEEE Journal of Solid-State Circuits, Vol.57, Issue. 4, Pages 1039-1048

7

[Apr. 2022]
T.-H. Kim, B. Song, I.-J. Jung, and S.-O. Jung, "A Sneak Current Compensation Scheme with Offset Cancellation Sensing Circuit for ReRAM-based Cross-point Memory Array," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.69, no.4, Pages 1583 - 1594

8

[Mar. 2022]
K. Cho, J, Park, K, Kim, T. W. Oh, and S.-O. Jung, "SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse with Bitline Charge Sharing for Near-Threshold Operation," IEEE Transactions on Circuits and Systems II, vol.69, no.3, Pages 1567 - 1571

9

[Oct. 2021]
D. H. Ko, T. W. Oh, S. Lim, S. K. Kim, and S.-O. Jung, "Comparative Analysis and Energy-efficient Write Scheme of Ferroelectric FET-Based Memory Cells," IEEE Access, vol.9, Pages 127895 - 127905

10

[Oct. 2021]
S. Joo, T. W. Oh, J. Y. Kim, S. Lee, B. M. Moon, K. Sohn, and S.-O. Jung, "High Accurate, Fully Digital Temperature Sensor With Curvature Correction," IEEE Sensors Journal, vol.21, no.19, Pages 21248 - 21258

11

[Jun. 2021]
J. Y. Kim, J. S. Lee, K. Kim, B. M. Moon, and S.-O. Jung, "A 0.166 pJ/b/pF, 3.5–5 Gb/s TSV I/O Interface with VOH Drift Control," IEEE Transactions on Circuits and Systems II, vol.68, no.6, Pages 1822-1826

12

[Jun. 2021]
S. M. Kim, B. Song and S.-O. Jung, "Imbalance-tolerant Bit-line Sense Amplifier for Dummy-less Open Bit-line Scheme in DRAM," IEEE Transactions on Circuits and Systems I: Regular Papers,vol.68, no.6, Pages 2546-2554

13

[Jun. 2021]
S. Choi, H. K. Ahn, B. Song, S. H. Kang and S.-O. Jung, "Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.68, no.6, Pages 2481-2493

14

[Apr. 2021]
J. Oh, J. Park, K. Cho, T. W. Oh, and S.-O. Jung, "Differential Read/Write 7T SRAM with Bit-Interleaved Structure for Near-Threshold Operation," IEEE Access, vol.9, Pages 64105-64115

15

[Apr. 2021]
K. Kim, T. W. Oh, and S.-O. Jung, "Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-efficient 6T SRAM" IEEE Access, vol.9, Pages 57393-57403

16

[Apr. 2021]
B. Song, S. Lim, S. H. Kang and S.-O. Jung, "Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell with Auto Write-Back Technique," IEEE Transactions on Information Forensics & Security, vol.16, Pages 2843-2853

17

[Apr. 2021]
S. K. Kim, T. W. Oh, S. Lim, D. H. Ko, and S.-O. Jung, "High-performance and Area-efficient Ferroelectric FET-based Nonvolatile Flip-Flops," IEEE Access, vol.9, Pages 35549-35561

18

[Apr. 2021]
K. W. Lee, H. K. Park, and S.-O. Jung, "Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.29, no.4, Pages 631-642

19

[Apr. 2021]
K. Kim, J. Y. Kim, B. M. Moon, and S.-O. Jung, "A 6.9-μm^2 3.26-ns 31.25-fJ Robust Level Shifter with Wide Voltage and Frequency Ranges," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.68, no.4, Pages 1433-1437

20

[Feb. 2021]
J. H. An, J. Y. Chun, H. K. Park, and S.-O. Jung, "All-Bit-Line Read Scheme with Locking Bit-Line and Amplifying Sense Node in NAND Flash", IEEE Access, Pages 28001-28011

21

[Feb. 2021]
H. Jeong, T. Kim, C. N. Park, H. Kim, T. Song, and S.-O. Jung, “A Wide-range Static Current Free Current Mirror based LS with Logic Error Detection for Near-threshold Operation," IEEE Journal of Solid-State Circuits, Vol.56, Issue. 2, Pages 554-565

22

[Jan. 2021]
T. Na, S. H. Kang, and S.-O. Jung, "STT-MRAM Sensing: A Review," IEEE Transactions on Circuits and Systems II, Vol. 68, Issue. 1, Pages 12-18

23

[Dec. 2020]
G. Kim, K. Kim, S. Choi, H. Jang, and S.-O. Jung, "Area- and Energy- Efficient STDP Learning Algorithm for Spiking Neural Network SoC" IEEE Access, Pages 216922-216932

24

[Dec. 2020]
H. K. Park, H. K. Ahn, and S.-O. Jung, "A novel matchline scheduling method for low power and reliable search operation in cross-point-array ternary CAM," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Issue. 12, Pages 2650-2657

25

[Oct. 2020]
S. M. Lee, S. Joo, J. Park, H. K. Ahn, and S.-O. Jung, "CNN Acceleration with Hardware-Efficient Dataflow for Super-Resolution," IEEE Access, Pages 187754-187765

26

[Oct. 2020]
T. H. Kim, H. Jeong, J. Park, H. Kim, T. Song, and S.-O. Jung, "An Embedded Level-shifting Dual-rail SRAM for High-speed and Low-power Cache," IEEE Access, Pages 187126-187139

27

[May. 2020]
K. Cho, J. Park, T. W. Oh, and S.-O. Jung , "One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, Issue. 5, Pages 1551-1561

28

[Apr. 2020]
J. Park, T. W. Oh, and S.-O. Jung, "pMOS Pass Gate Local Bitline SRAM Architecture with Virtual VSS for Near-Threshold Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Issue. 4, Pages 1079-1083

29

[Mar. 2020]
S. Lim, B. Song, and S.-O. Jung , "Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability," IEEE Transactions on Information Forensics & Security, Vol. 15, Pages 2798-2807

30

[Jan. 2020]
J. Park, J.-H. Park, and S.-O. Jung , "Current Measurement Transducer Based on Current-to-Voltage-to-Frequency Converting Ring Oscillator with Cascade Bias Circuit," MDPI Sensors

31

[Nov. 2019]
T. Na, B. Song, S. Choi, J. P. Kim, S. H. Kang, and S.-O. Jung, “Offset-Canceling Single-Ended Sensing Scheme with One-Bit-Line Precharge Architecture for Resistive Non-Volatile Memory in 65nm CMOS," IEEE Transactions on Very Large Scale Integration System, Vol. 27, Issue. 11, Pages 2548-2555

32

[Oct. 2019]
S.M. Kim, B. Song, and S.-O. Jung, “Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM," IEEE Transactions on Very Large Scale Integration System, Vol. 27, Issue. 10, Pages 2413-2422

33

[Aug. 2019]
H. Jeong, J. Park, S.C. Song, and S.-O. Jung, “Self-Timed Pulsed Latch for Low Voltage Operation with 77% Hold Time Reduction," IEEE Journal of Solid-State Circuits, Vol. 54, No. 8, Pages 2304-2315

34

[Aug. 2019]
B. Song, S. Choi, S. H. Kang, and S.-O. Jung , "Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Issue. 8, Pages 2963-2972

35

[May. 2019]
J. Ko, Y. Yang, J. Kim, C. Lee, Y.-S. Min, J. Chun, M.-S. Kim, and S.-O. Jung, “Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory," IEEE Transactions on Very Large Scale Integration System, Vol. 27, No. 8, Pages 1828-1839

36

[Apr. 2019]
H. K. Park, T. H. Choi, H. K. Ahn, and S.-O. Jung, “Thermoelectric cooling read for resolving read disturb with inrush current issue in OTS-PRAM," IEEE Transactions on Nanotechnology, Vol. 18, Pages 421-431

37

[Mar. 2019]
H. Jeong, S. Oh, T. W. Oh, H. Kim, C. N. Park, W. Rim, T. Song, and S.-O. Jung, “Bitline Charge-Recycling SRAM Write Assist Circuitry for Improvement and Energy Saving," IEEE Journal of Solid-State Circuits, Vol. 54, Issue. 3, Pages 896-906

38

[Feb. 2019]
S. Choi, H. K. Ahn, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung, “A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 2, Pages 387-397

39

[Jan. 2019]
T. H. Choi, T. W. Oh, and S.O. Jung, “Parasitic RC Aware Delay Corner Model for Sub-10-nm Logic Circuit Design,” IEEE Transactions on Electron Devices, Vol. 66, Issue. 1, Pages 191-199

40

[Jun. 2018]
D.-H. Jung, K. Kim, S. Joo, and S.-O. Jung, "0.293 mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter with Area-efficient Time-domain-based Controller in 0.35 μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 53, No. 6, Pages 1844-1855

41

[Jun. 2018]
D.-H. Jung, K. Ryu, J.-H. Park, and S.-O. Jung, "All-Digital Process-Variation-Calibrated Timing Generator for ATE with 1.95-ps Resolution and Maximum 1.2-GHz Test Rate," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 6, Pages 1015-1025

42

[Apr. 2018]
H. Jeong, T. W. Oh, S. C. Song, and S.-O. Jung, "Sense Amplifier-Based Flip Flop with Transition Completion Detection for Low Voltage Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 4, Pages 609-620

43

[Jan. 2018]
T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung , "Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 1, Pages 163-174

44

[Dec. 2017]
J.-H. Park, D.-H. Jung, and S.-O. Jung , "GRO-TDC With Gate-Switch Based Delay Cell Halving Resolution Limit," International Journal of Circuit Theory and Applications, Vol. 45, No. 12, Pages 2211-2225

45

[Oct. 2017]
T. W. Oh, H. Jeong, J. Park, and S.-O. Jung , "Pre-charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 10, Pages 2737-2747

46

[Aug. 2017]
T. H. Choi, H. Jeong, Y. Yang, J. Park, and S.-O. Jung , "SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 8, Pages 2063-2072

47

[Jun. 2017]
B. Song, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, "A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and Compact Area," IEEE Transactions on Circuits and Systems II, Vol. 64, No. 6, Pages 700-704

48

[Jun. 2017]
J. Ko, Y. Yang, J. Kim, Y. Oh, H. K. Park, and S.-O. Jung, "Incremental Bit Line Voltage Sensing Scheme with Half-Adaptive Threshold Reference Scheme in MLC PRAM," IEEE Transactions on Circuits and Systems I, Vol. 64, No. 6, Pages 1444-1455

49

[Mar. 2017]
T. W. Oh, H. Jeong, K. Kang, J. Park, Y. Yang, and S.-O. Jung, "Power-Gated 9T SRAM Cell for Low-Energy Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 3, Pages 1183-1187

50

[Feb. 2017]
T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung, "Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 52, No. 2, Pages 496-504

51

[Nov. 2016]
Y.-J. An, D.-H. Jung, K. Ryu, H. S. Yim, and S.-O. Jung, "All-Digital On-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 11, Pages 3232-3242

52

[Nov. 2016]
H. Jeong, J. Park, T. W. Oh, W. Rim, T. Song, G. Kim, H-S. Won, and S.-O. Jung, "Bit-line Precharging and Preamplifying Switching PMOS for High-Speed Low-Power SRAM," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 11, Pages 1059-1063

53

[Oct. 2016]
K. Kim, H. Jeong, J. Park, and S.-O. Jung, "Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 10, Pages 964-968

54

[Sep. 2016]
T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, "Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 9, Pages 2993-2997

55

[Sep. 2016]
S. Choi, T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung, "Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 9, Pages 2851-2860

56

[Jul. 2016]
Y. Yang, H. Jeong, S. C. Song, J. Wang, G. Yeap, S.-O. Jung, "Single Bit-line 7T SRAM Cell for Near-threshold Voltage Operation with Enhanced Performance and Energy in 14 nm FinFET Technology," IEEE Transactions on Circuits and Systems I, Vol. 63, No. 7, Pages 1023-1032

57

[Jun. 2016]
T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, "Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM," IEEE Transactions on Circuits and Systems II, Vol. 63, No. 6, Pages 578-582

58

[Apr. 2016]
D.-H. Jung, K. Kim, and S.-O. Jung, “Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm,” IEICE Electronics Express, Vol. 13, No. 12, Pages 1-9

59

[Apr. 2016]
K. Ryu, J. Jung, D.-H. Jung, J. H. Kim, and S.-O. Jung, "High-speed, Low-power, and Highly Reliable Frequency Multiplier for DLL-based Clock Generator," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 4, Pages 1484-1492

60

[Apr. 2016]
T. Na, J. Kim, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung, "An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 4, Pages 1361-1370

61

[Apr. 2016]
K. Kang, H. Jeong, Y. Yang, J. Park, K. Kim, and S.-O. Jung, "Full-Swing Local Bit-Line SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 4, Pages 1342-1350

62

[Mar. 2016]
D.-H. Jung, K. Ryu, J. Park, and S.-O. Jung, "All-Digital 90° Phase-Shift DLL with Dithering Jitter Suppression Scheme," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 3, Pages 1015-1024

63

[Dec. 2015]
G. Kaushal, H. Jeong, S. Maheshwaram, S. K. Manhas, S. Dasgupta, and S.-O. Jung, "Low power SRAM design for 14nm GAA Si-nanowire technology," Microelectronics Journal, Vol. 46, No. 12, Pages 1239-1247

64

[Dec. 2015]
T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung, "A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory," IEEE Transactions on Circuits and Systems II, Vol. 62, No. 12, Pages 1109-1113

65

[Nov. 2015]
D.-H. Jung, Y. An, K. Ryu, J. Park, and S.-O. Jung, "All-Digital Fast-Locking Delay-Locked Loop Using Cyclic-Locking Loop for DRAM," IEEE Transactions on Circuits and Systems II, Vol. 62, No. 11, Pages 1023-1027

66

[Nov. 2015]
Y. Yang, J. Park, S. C. Song, J. Wang, G. Yeap, S.-O. Jung, "Single-ended 9T SRAM Cell for Near-threshold Voltage Operation with Enhanced Read Performance in 22-nm FinFET Technology" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 11, Pages 2748-2752

67

[Aug. 2015]
J. Ko, J. Kim, Y. Choi, H. K. Park, and S.-O. Jung, "Temperature-Tracking Sensing Scheme with Adaptive Precharge and Noise Compensation Scheme in PRAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 8, Pages 2091-2102

68

[Aug. 2015]
Y. An, K. Ryu, D. Jung, S. Woo and S.-O. Jung, "An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 8, Pages 1508-1517

69

[Jul. 2015]
H. Jeong, T. Kim, T. Song, G. Kim and S.-O. Jung, "Trip-point Bit-line Precharge Sensing Scheme for Singleended SRAM" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 7, Pages 1370-1374

70

[Jul. 2015]
B. Song, T. Na, J. Kim, J. P. Kim, S. H. Kang and S.-O. Jung, "Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 7, Pages 1776-1784

71

[Jun. 2015]
Y. Yang, J. Park, S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, "SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 6, Pages 1538-1545

72

[Jun. 2015]
H. Jeong, K. Kang, T. Song, G .Kim, H.-S. Won, and S.-O. Jung, " Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 6, Pages 1555-1563

73

[Jun. 2015]
H. Jeong , Y. Yang, S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, "Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region" IEEE Transactions on Electron Devices, Vol. 62, No. 6, Pages 1754-1759

74

[Jun. 2015]
J. Park, Y. Yang, H. Jeong S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, "Design of a 22-nm FinFET-based SRAM with Read Buffer for Near-Threshold Voltage Operation" IEEE Transactions on Electron Devices, Vol. 62, No. 6, Pages 1698-1704

75

[Apr. 2015]
H. Jeong, T. Kim, Y. Yang, T. Song, G .Kim, H.-S. Won, and S.-O. Jung, "Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM" IEEE Transactions on Circuits and Systems I, Vol. 62, No. 4, Pages 1062-1070

76

[Apr. 2015]
H.C. Kang, J. Kim, H.W. Jung, Y.H. Yang, and S.-O. Jung, "Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory" IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 4, Pages 752-765

77

[Mar. 2015]
J.-H. Park, H. Kang, D.-H. Jung, K. Ryu and S.-O. Jung, "Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs," IEEE Transactions on Very Large Scale Integration systems, Vol. 23 , No. 3 , Pages 413-421

78

[Dec. 2014]
T. Na, J. Kim, J. P. Kim, S. H. Kang and S.-O. Jung, "Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM," IEEE Transactions on Circuits and Systems I, Vol. 61 , No. 12 , Pages 3376-3385

79

[Jul. 2014]
T. Na, J. Kim, J. P. Kim, S. H. Kang and S.-O. Jung, "An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM," IEEE Transactions on Very Large Scale Integration systems, Vol.22 , No.7 , Pages 1620-1624

80

[Jul. 2014]
J. Kim, K. Ryu, J. P. Kim, S.H., Kang and S.O. Jung “An STT-MRAM Sensing Circuit with Self-Body Biasing in Deep Submicron Technologies," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22 , No. 7 , Pages 1630-1634

81

[June. 2014]
H. Jeong, Y. Yang, J.Lee, J. Kim, and S.O. Jung “One-sided Static Noise Margin and Gaussian-tail-fitting Method for SRAM," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 6, Pages 1262-1269

82

[Apr. 2014]
Y.D. Jung, J. Kim, K. Ryu, J.P. Kim, S.H. Kang and S.O. Jung, “An MTJ-Based Non-Volatile Flip-Flop for High Performance SoC,” International Journal of Circuit Theory and Applications, Vol. 42, No. 4, Pages 394-406

83

[Mar. 2014]
J. Kim, T. Na, J. P. Kim, S. H. Kang and S.-O. Jung, "A Split-Path Sensing Circuit for Spin Torque Transfer MRAM (STT-MRAM)," IEEE Transactions on Circuits and Systems II, Vol. 61, No. 3, Pages 193-197

84

[Feb. 2014]
T. Na, S. H. Woo, J. Kim, H. W. Jeong, and S.-O. Jung “Comparative Study of Various Latch-Type Sense Amplifiers," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 2, Pages 425-429

85

[Jan. 2014]
K. Ryu, D.H. Jung, and S.O. Jung "Process Variation Calibrated Multi-Phase Delay Locked Loop with a Loop-Embedded Duty Cycle Correctort," IEEE Transactions on Circuits and Systems II, Vol. 61, No. 1, Pages 1-5

86

[Jan. 2014]
Y.J. An, K. Ryu, D.H. Jung, S.H. Woo and S.O. Jung "An Energy Efficient Time-domain Temperature Sensor for Low-power On-chip Thermal Management," IEEE Sensors Journal, , Vol. 14, pp.104-110, Jan. 2014.

87

[Jul. 2013]
M. Kang, J. Kim, Y.H. Yang, and S.O. Jung, “Dynamic Mixed Serial-Parallel Content Addressable Memory (DMSP CAM),” International Journal of Circuit Theory and Applications, Vol. 41, No. 7, Pages 721-731

88

[Jul. 2013]
J.H. Park, D.H. Jung, K. Ryu, and S.O. Jung “An ADDLL for Clock-Deskew Buffer in High-Performance SoCs," IEEE Transactions on Very Large Scale Integration Systems, Vol.21 , No.7 , Pages 1368-1373

89

[Nov. 2012]
K. Ryu, J. Kim, J.W. Jung, J.P. Kim, S.H. Kang, S.O. Jung “ A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop,” IEEE Transactions on Very Large Scale Integration Systems, Vol.20 , No.11 , Pages 2044-2053

90

[Oct. 2012]
H.C. Kang, K. Ryu, D.H. Jung, D.H. Lee, W. Lee, S.H. Kim, J.R. Choi, and S.O. Jung, “Process Variation Tolerant All-Digital 90' Phase Shift DLL for DDR3 Interface,” IEEE Transactions on Circuits and Systems I, Vol. 59, No. 10 , Pages 2186-2196

91

[Oct. 2012]
Y. Yang, H. Jeong, F. Yang, J. Wang, G. Yeap, and S.O. Jung, “Read-Preferred SRAM Cell with Write-Assist Circuit using Back-Gate ETSOI Transistors in 22-nm Technology,” IEEE Transactions on Electron Devices, Vol. 59, No. 10, Pages 2575-2581

92

[Sep. 2012]
K. Ryu, D.H. Jung, and S.O. Jung, “A DLL with Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator,” IEEE Transactions on Circuits and Systems I, Vol.59 , No.9 , Pages 1860-1870

93

[Jan. 2012]
J. Kim, K.H. Ryu, S.H. Kang, and S.O. Jung, “A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM),” IEEE Transactions on Very Large Scale Integration Systems, Vol. 20, No. 1, Pages 181-186

94

[Sep. 2011]
M. Kang, H. K. Park, J. Wang, G. Yeap, and S.O. Jung, “Asymmetric Independent-Gate MOSFET SRAM for High Stability,” IEEE Transactions on Electron Devices, Vol. 58, No. 9, Pages 2959-2965

95

[Mar. 2011]
Chulhyun Park,Youngkyu Song, Junghan Kang, Seong-Ook Jung, Ilgu Yun, "Effects of Electrical Characteristics on the Non-Rectangular Gate Structures Variations for the Multi-finger MOSFETs," IEEE Transactions on Components and Packaging Technologies, Vol.1, No. 3, Pages 352-358

96

[Mar. 2011]
J.H. Song, J.S. Kim, S.H. Kang, S.S. Yoon and S.O. Jung, “Sensing Margin Trend with Technology Scaling in MRAM,” International Journal of Circuit Theory and Applications, Vol. 39, No. 3, Pages 313-325

97

[Nov. 2010]
D.H. Jung, K. Ryu, and S.O. Jung, “A 90° Phase-Shift DLL with Closed-Loop DCC for High-Speed Mobile DRAM Interface,” IEEE Transactions on Consumer Electronics, Vol. 56, No. 4, Pages 2400-2405

98

[Nov. 2010]
M. Kang, S.C. Song, S.H. Woo, H.K. Park, M.H. Abu-Rahma, L. Ge, B.M. Han, J. Wang, G. Yeap, and S.O. Jung, "FinFET SRAM Optimization with Fin Thickness and Surface Orientation,” IEEE Transactions on Electron Devices, Vol. 57, No. 11, Pages 2785-2793

99

[Nov. 2010]
S.-H Woo, H.C. Kang, K. Park, and S.O. Jung, “Offset voltage estimation model for latch-type sense amplifiers” IET Circuits, Devices, and Systems, Vol. 4, No. 6, Pages 503-513

100

[Aug. 2010]
K. Ryu, D.H. Jung, and S.O, Jung, “A DLL Based Clock Generator for Low-Power Mobile SoCs,” IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, Pages 1950-1956

101

[Jun. 2010]
J. Kim, J.H. Song, S.H. Kang, S.S. Yoon and S.O. Jung, “Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits,” IEICE Transactions on Electronics, Vol. E93-C, No. 6, Pages 912-921

102

[July 2009]
M.H. Hwang, S.O. Jung and K. Roy, "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation," IEEE Transactions on Circuits and Systems-I, Vol. 56. No. 7, Pages 1428-1441

103

[Jan 2009]
M. Kang and S.O. Jung, "Serial-Parallel Content Addressable Memory with A Conditional Driver (SPCwCD)," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E92-A, No.1, Pages 318-321

104

[Sep 2008]
H. Nho, S.S. Yoon, S.S. Wong and S.O. Jung, "Numerical Estimation of Yield in Sub-100nm SRAM Design using Monte Carlo Simulation," IEEE Transactions on Circuits and System- II, Vol. 55. No. 9, Pages 907-911

105

[Mar 2008]
S.O. Jung and S.S. Yoon, "Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E91-A, No.3, Pages 895-898

106

[Aug 2007]
H. Nho, S.S. Yoon, S. Wong and S.O. Jung, "Statistical Simulation Methodology for sub-100nm Memory Design," IEEE Electronics Letters, Vol. 43, No. 16, Pages 869-870

107

[Aug 2005]
G. Yang, S.O. Jung, K.H. Baek, S.H. Kim, S. Kim and S.M. Kang, "A 32-bit Carry Lookahead Adder Using Dual-Path All-N Logic," IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 8, Pages 992-996

108

[Oct 2003]
K.W. Kim, S.O. Jung, T.W. Kim, P. Saxena, C.L. Liu and S.M. Kang, "Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique," IEEE Transactions on Very Large Scale Integration Systems, Vol. 11, No. 5, Pages 879-887

109

[Apr 2003]
K.W. Kim, S.O. Jung, T.W. Kim and S.M. Kang, "Minimum Delay Optimization for Domino Logic Circuits – A Coupling-Aware Approach," ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 2, Pages 203-213

110

[Feb 2003]
K.W. Kim, S.O. Jung, U. Narayanan, C.L. Liu and S.M. Kang, "Noise-Aware Interconnect Power Optimization in Domino Logic Synthesis," IEEE Transactions on Very Large Scale Integration Systems, Vol. 11, No. 1, Pages 79-89

111

[Jan 2003]
S.O. Jung, K.W. Kim and S.M. Kang, "Timing Constraints for Domino Logic Gates with Timing Dependent Keepers," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 1, Pages 96-103

112

[Oct 2002]
S.O. Jung, K.W. Kim and S.M. Kang, "Noise Constrained Transistor Sizing and Power Optimization for Dual Vt Domino Logic," IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 5, Pages 532-541

113

[Aug 2002]
S.O. Jung and S.M. Kang, "High Performance Dynamic Logic Incorporating Gate Voltage Controlled Keeper Structure for Wide Fan-In Gate," IET Electronics Letters, Vol. 38, No. 16, Pages 852-853

114

[Jun 2002]
C. Kim, S.O. Jung, K.H. Baek and S.M. Kang, "High-Speed CMOS Circuits with Parallel Dynamic Logic and Speed-enhanced Skewed Static Logic," IEEE Transactions on Circuits and Systems Part II : Analog and Digital Signal Processing, Vol. 49, No. 6, Pages 434-439

115

[Jun 2001]
K.W. Kim, S.O. Jung, T.W. Kim and S.M. Kang, "Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits," IET Electronics Letters, Vol. 37, No. 13, Pages 813-814

116

[Mar 2000]
S.O. Jung and S.M. Kang, "Modular Charge Recycling Pass transistor Logic (MCRPL)," IET Electronics Letters, Vol. 36, No. 5, Pages 404-405