 |
 |
| 1 |
[Accepted]
M. Yeo, K. Cho, G. Kim, J. Oh, S. K. Kim, K. Baek, S. J. Yei, and S.-O. Jung “Self-Enabled Write Assist Cells for High-Density SRAM in Resistance Dominated Technology Node", International Solid-State Circuits Conference, 2024.
|
| 2 |
[Jun. 11-16, 2023]
S. K. Kim, K. Cho, K. Baek, H. Kim, M. Kim, D. Seo, S. Baeck, S. Lee, and S.-O. Jung “A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications", Symposium on VLSI Technology and Circuits, 2023.
|
| 3 |
[Jun. 11-16, 2023]
T. Kim, J. Y. Kim, J. You, K. Kim, B. M. Moon, K. Sohn, and S.-O. Jung “A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC", Symposium on VLSI Technology and Circuits, 2023.
|
| 4 |
[Sep. 19-22, 2022]
S. Lim, Y. Goh, Y. Lee, D. Ko, J. Hwang, M. Kim, Y. Jeong, H. Shin, S. Jeon, and S.-O. Jung, “A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF", European Solid State Device Research Conference (ESSDERC) / European Conference on Solid-State Circuits (ESSCIRC) |
| 5 |
[Sep. 19-22, 2022]
S. Lee, S. Joo, H. K. Ahn, J. Lee, D. Kim, B. Ham, and S.-O. Jung, “SIF-NPU: a 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution", European Solid State Device Research Conference (ESSDERC) / European Conference on Solid-State Circuits (ESSCIRC) |
| 6 |
[Jun. 12-17, 2022]
J. Y. Kim, T. Kim, J. You, K. Kim, B. M. Moon, K. Sohn, and S.-O. Jung “A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM", Symposium on VLSI Technology and Circuits, 2022.
|
| 7 |
[Jun. 12-17, 2022]
K. Cho, G. Kim, J. Oh, K. Kim, C. Sim, Y. Bae, M. Kim, S. Baeck, T. Song, and S.-O. Jung “ A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications", Symposium on VLSI Technology and Circuits, 2022.
|
| 8 |
[Dec. 13-15, 2021]
Y. Goh, J. Hwang, M. Kim, M. Jung, S. Lim, S.-O. Jung, and S. Jeon “High Performance and Self-rectifying Hafina-based Ferroelectric Tunnel Junction for Neuromorphic Computing and TCAM Applications", IEEE International Electron Devices Meeting (IEDM), 2021. |
| 9 |
[June. 13-19, 2021]
K. Cho, H. Choi, I.-J. Jung, J. Oh, T. W. Oh, K. Kim, G. Kim, T. Choi, C. Sim, T. Song, and S.-O. Jung “SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effect Increased with Technology Scaling", Symposium on VLSI Technology and Circuits, 2021. |
| 10 |
[Dec. 12-18, 2020]
H. Han, R. Choi, S.-O. Jung, S. W. Chung, B. J. Cho, S. C. Song, and C. Choi “Low Temperature and Ion-Cut Based Monolithic 3D Process Integration Platform Incorporated with CMOS, RRAM and Photo-Sensor Circuits", IEEE International Electron Devices Meeting (IEDM), 2020. |
| 11 |
[Oct. 11-14, 2020]
K. Lee, H. K. Park, and S.-O. Jung “A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-Pram,” IEEE International Symposium on Circuits and Systems (ISCAS), 2020. |
| 12 |
[July. 3-6, 2020]
J. Kim, J. Park, S. Joo, and S.-O. Jung, “Efficient Hardware Implementation of STDP for AER Based Large-Scale SNN Neuromorphic System,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2020. |
| 13 |
[July. 3-6, 2020]
J. H. An, H. K. Park, T. W. Oh, and S.-O. Jung, “A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2020. |
| 14 |
[June. 23-26, 2019]
W. Seo, B. Song, and S.-O. Jung, “Reliable Latency Extraction with NVSim Revision in Emerging NVM,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2019. |
| 15 |
[June. 23-26, 2019]
J. Sim, S. Joo, and S.-O. Jung, “Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2019. |
| 16 |
[June. 9-14, 2019]
T.H. Choi, H.W. Choi, J.H. Choi, H.T. Choo, H.C. Jung, H.Y. Kim, T.J. Song, J.O. Kye, and S.-O. Jung, “Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology,” Symposium on VLSI Technology and Circuits, 2019. |
| 17 |
[Dec. 9-12, 2018]
B. Yoo, K. Kim, and S.-O. Jung, “Triplet-Based Spike Timing Dependent Plasticity Circuit Design for Three-Terminal Spintronic Synapse,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2018. |
| 18 |
[Dec. 9-12, 2018]
H. K. Park, T. W. Oh, and S.-O. Jung, “A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2018. |
| 19 |
[July. 4-7, 2018]
H. K. Choi, T. H. Kim, and S.-O. Jung, “Evaluation of the Offset Voltage Variation at the FinFET SRAM Voltage Latched-type Sense Amplifier,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2018. |
| 20 |
[July. 4-7, 2018]
S. Lim, H. Jang, B. Song, and S.-O. Jung, “MTJ-based Arbiter PUF with Write Back Technique for Improved Stability,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2018. |
| 21 |
[July. 4-7, 2018]
J. Y. Kim, K. Kim, and S.-O. Jung, “A 0.81ns 26.7fJ/cycle Extremely Low Energy Delay Product Level Shifter,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2018. |
| 22 |
[July. 2-5, 2018]
S. Kim, B. Song, T. W. Oh, and S.-O. Jung, “Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM,” Conference on PhD Research in Microelectronics and Electronics (PRIME), 2018. |
| 23 |
[May. 27-30, 2018]
T. W. Oh and S.-O. Jung, “SRAM Cell with Data-Aware Power-Gating Write-Assist for Near-Threshold Operation,” IEEE International Symposium on Circuits and Systems (ISCAS), 2018. |
| 24 |
[May. 27-30, 2018]
T. H. Choi, H. Jeong, J. Park, Y. Yang, and S.-O. Jung, “SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis,” IEEE International Symposium on Circuits and Systems (ISCAS), 2018. |
| 25 |
[Jan. 24-27, 2018]
S. Joo, Y.-J. An, T. W. Oh, and S.-O. Jung, “Comparative Analysis of MCU memory for IoT Application,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 26 |
[Jan. 24-27, 2018]
H. K. Ahn, S. Choi, and S.-O. Jung, “Evaluation of STT-MRAM L3 Cache in 7nm FinFET Process,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 27 |
[Jan. 24-27, 2018]
J. Park, H. Jeong, and S.-O. Jung, “Pulsed PMOS Sense Amplifier for High Speed Single-Ended SRAM,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 28 |
[Jan. 24-27, 2018]
S. M. Kim, T. W. Oh, and S.-O. Jung, “Sensing Voltage Compensation Circuit for Low-Power DRAM Bit-Line Sense Amplifier,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 29 |
[Jan. 24-27, 2018]
H.-K. Park, B. Song, and S.-O. Jung, “Low Search Power and High Reliability 13T-4R MTJ based Nonvolatile Ternary Content-Addressable Memory,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 30 |
[Jan. 24-27, 2018]
T. H. Choi, H. Jeong, and S.-O. Jung, “Fast Monte-Carlo Analysis Method of Ring Oscillators with Neural Networks,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 31 |
[Jan. 24-27, 2018]
J. Y. Chun, H.-K Park, B. Song, and S.-O. Jung, “Stepwise Controlled Voltage Sensing Scheme for High-Density ReRAM with Multi Level Cell,” International Conference on Electronics, Information, and Communication (ICEIC) 2018. |
| 32 |
[Jul. 2-5, 2017]
S. Joo, K. Kim, D.-H. Jung, and S.-O. Jung, "DC-DC Boost Converter Using Offset-Controlled Zero Current Sensor for Low Loss Thermoelectric Energy Harvesting Circuit," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2017. |
| 33 |
[Jul. 2-5, 2017]
K. Kim, J.-H. Park, J. Park, and S.-O. Jung, "Constantly Current-matched Charge Pump for Low Voltage PLLs Using Body Voltage Feedback," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2017. |
| 34 |
[Jul. 2-5, 2017]
H. K. Ahn, D.-H. Jung, and S.-O. Jung, "Buck Converter for Improved Transient Response with Shot Current Generator," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2017. |
| 35 |
[Jul. 2-5, 2017]
H. J. Kim, T. W. Oh, J. Park, and S.-O. Jung, "Optimal Design of Device Parameters for Improving SRAM Bitcell Margin 14nm FinFET Technology," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2017. |
| 36 |
[Jan. 11-14, 2017]
J. S. Park, J. Park, and S.-O. Jung, “Analysis on Full Adder with Restoring Function in Nominal and Low Supply Voltage,” International Conference on Electronics, Information, and Communication (ICEIC) 2017. |
| 37 |
[Oct. 26-28, 2016]
J. Park, H. Jeong, H. J. Kim, and and S.-O. Jung, “Low Power SRAM Bitcell Design for Near-Threshold Operation,” IEEE/IEIE International Conference on Consumer Electronics Asia (ICCE-Asia), 2016. |
| 38 |
[Oct. 23-26, 2016]
B. Yoo, T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung, “Equalization Scheme Analysis for High-density Spin Transfer Torque Random Access Memory,” International SoC Design Conference, 2016. |
| 39 |
[Jul. 10-13, 2016]
S. Oh, H. Jeong and S. -O. Jung, "Comparative Analysis on Replica Techniques for Bit-Line Tracking in 14-nm node," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2016 |
| 40 |
[Jul. 10-13, 2016]
T. Kim, H. Jeong and S. -O. Jung, "Evaluation of Threshold Voltage Extraction Methods in Deep-submicron Technology," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2016 |
| 41 |
[May. 22-25, 2016]
S. Choi, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, “Area-Optimal Sensing Circuit Designs in Deep Submicrometer STT-RAM,” IEEE International Symposium on Circuits and Systems (ISCAS), 2016. |
| 42 |
[May. 22-25, 2016]
J. Ko, Y. Yang, J. Kim, C. A. Lee, Y.-S. Min, J. Chun, M. Kim and S.-O. Jung, “WL Under-Driving Scheme with Decremental Step Voltage and Incremental Step Time for High-Capacity NAND Flash Memory,” IEEE International Symposium on Circuits and Systems (ISCAS), 2016. |
| 43 |
[Jan. 27-30, 2016]
J. Park, H. Jeong, and S.-O. Jung, “10T SRAM with Bit-Interleaving Structure for Near-Threshold Operation,” International Conference on Electronics, Information, and Communication (ICEIC) 2016. |
| 44 |
[Jan. 27-30, 2016]
J. Ko, Y. Yang, J. Kim, C. A. Lee, Y.-S. Min, J. Chun, M. Kim and S.-O. Jung, “Comparative Study of WL Driving Method for High-Capacity NAND Flash Memory,” International Conference on Electronics, Information, and Communication (ICEIC) 2016. |
| 45 |
[Dec. 6-9, 2015]
T. Na, H. Jeong, J. P. Kim, S.H. Kang, and S.O. Jung, “Efficiency Analysis of Importance Sampling in Deep Submicron STT-Ram Design Using Uncontrollable Industry-Compatible Model Parameter,”
IEEE International Conference on Electronics, Circuits, & Systems (ICECS), 2015. |
| 46 |
[Jul. 22-24, 2015]
B. Song, T. Na, J. P. Kim, S.H. Kang, and S.O. Jung, “Reference-Circuit Analysis for High-Bandwidth Spin Transfer Torque Random Access Memory,” International Symposium on Low Power Electronics and Design (ISLPED), 2015. |
| 47 |
[Dec. 7-10, 2014]
H. Jeong, T. Kim, T.S, G.K, and S.O. Jung, “Pseudo NMOS Based Sense Amplifier for High Speed Single-Ended SRAM,” International Conference on Electronics Circuits and Systems, 2014. |
| 48 |
[Nov. 3-6, 2014]
G. Kaushal , R. Vaddi, S. K, S. N. Rao, V. K, R. Ramya, S. Shaik, H. Jeong, and S. O. Jung, “Design and Performance Benchmarking of Steep-Slope Tunnel Transistors for Low Voltage Digital and Analog Circuits Enabling Self-Powered SOCs,” International SoC Design Conference, 2014. |
| 49 |
[Nov. 3-6, 2014]
B. Song, T. Na, H. Jeong, S. H. Kang, J. P. Kim and S. O. Jung, “Comparative Analysis of Using Planar MOSFET and FinFET as Access Transistor of STT-RAM Cell in 22-nm Technology Node,” International SoC Design Conference, 2014. |
| 50 |
[Jun. 1-5, 2014]
T. Na, K. Ryu, J. Kim, J. P. Kim, S. H. Kang and S.-O. Jung, “High-Performance Low-Power Magnetic Tunnel Junction Based Non-Volatile Flip-Flop,” IEEE International Symposium on Circuits and Systems, 2014. |
| 51 |
[Jan. 15-18, 2014]
H. Jeong, T. Kim, T. Song, G. Kim, and S.O. Jung, “Half Bit-line Voltage Sensing Amplifier For High Speed Single-Ended SRAM Sensing,” International Conference on Electronics, Information and Communication, 2014.
|
| 52 |
[Nov. 17-19, 2013]
B. Song, T.Na, J. Kim, S.H. Kim, J.P. Kim and S.O. Jung, “Sensing Circuit Optimization Using Different Type of Transistors for Deep Submicron STT-RAM,” International SoC Design Conference, 2013. |
| 53 |
[Nov. 17-19, 2013]
K. Kang, H.Jeong, J. Lee, and S.O. Jung, “Comparative Analysis of 1:1:2 and 1:2:2 FinFET SRAM Bit-Cell Using Assist Circuit,” International SoC Design Conference, 2013. |
| 54 |
[Nov. 17-19, 2013]
D.H. Jung, H.Jeong, T. Song, G. Kim and S.O. Jung, “Source Follower Based Single Ended Sense Amplifier for Large Capacity SRAM Circuit,” International SoC Design Conference, 2013. |
| 55 |
[Sep. 23-25, 2013]
D.H. Jung, K. Ryu, J.H. Park, W. Lee, and S.O. Jung, “All-Digital 90º Phase-Shift DLL with a Dithering Jitter Suppression Scheme,” IEEE Custom Integrated Circuits Conference, 2013. |
| 56 |
[Sep. 16-20, 2013]
K. Ryu, D. Jung, and S.O. Jung, "All-Digital Process-Variation-Calibrated Timing Generator for Ate with 1.95-Ps Resolution and a Maximum 1.2-GHz Test Rate," 2013 European Solid-State Circuits Conference, Pages
|
| 57 |
[Jun. 30 - Jul. 3, 2013]
J.-H Park, K. Ryu, D.-H Jung, and S.-O. Jung, "A Cyclic TDC Based On a Successive Approximation Method," International Technical Conference on Circuits/Systems, Computers and Communications, 2013, Pages
|
| 58 |
[Jun. 30 - Jul. 3, 2013]
J. Lee, H. Jeong, K. Kang, Y. Yang, J. Kim, and S.O. Jung, "Read and Write Yield Improvement of FinFET Based SRAM Using Non-Minimal Gate Length," International Technical Conference on Circuits/Systems, Computers and Communications, 2013, Pages
|
| 59 |
[Jun. 30 - Jul. 3, 2013]
J. Kim, K. Ryu, D. -H. Jung, and S. -O. Jung, "A High Tracking Speed DC-DC Buck Converter Using Separated Capacitor," International Technical Conference on Circuits/Systems, Computers and Communications, 2013, Pages
|
| 60 |
[May. 19-23, 2013]
T. Na, K. Ryu, J. Kim, S. H. Kang and S.-O. Jung, “A Comparative Study of STT-MTJ Based Non-Volatile Flip-Flops,” IEEE International Symposium on Circuits and Systems, 2013, Pages
|
| 61 |
[Mar. 17-18, 2013]
Y. H. Yang, J. H. Park, S. C. Song, F. Yang, J. Wang, G. Yeap, and S. O. Jung, “Comparative Study for SRAM Cells in Near and Sub-threshold Region,” China Semiconductor Technology International Conference (CSTIC) 2013, Pages
|
| 62 |
[Jan. 30 - Feb. 2, 2013]
K. Ryu, D.H. Jung, and S.O. Jung, “A High Speed, Energy and Area Efficient Counter Including Carry Look-Ahead Block,” International Conference on Electronics, Information and Communication, 2013, Pages
|
| 63 |
[Jan. 11-14, 2013]
Y.J. An, K. Ryu, D.H. Jung, S.H. Woo and S.O. Jung, “A 0.67nJ/S Time-domain Temperature Sensor for Low Power On-chip Thermal Management,” International Conference on Consumer Electronics, 2013, Pages 574-575 |
| 64 |
[Dec. 9-12, 2012]
H.W. Jeong, Y.H. Yang, J.H. Lee, J.S. Kim and S.O. Jung, “Static Read Stability and Write Ability Metrics in FinFET based SRAM Considering Read and Write Assist Circuits,” International Conference on Electronics, Circuits, and Systems, 2012,
Pages 833-836
|
| 65 |
[Nov. 4-7, 2012]
J. Park, I. Lee, Y.-S. Park, S.-G. Kim, K.H. Ryu, D.H. Jung, K. Jo, C. K. Lee, H. Yoon, S.O. Jung and S. Kang, “Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment” International SoC Design conference, 2012, Pages,
|
| 66 |
[Nov. 4-7, 2012]
J. Lee, H. Jeong, Y.H. Yang, J.S. Kim and S.O. Jung, “Impact of fin thickness and height on Read Stability / Write Ability in Tri-Gate FinFET based SRAM,” International SoC
Design conference, 2012, Pages,
|
| 67 |
[Sep. 17-21, 2012]
D.H. Jung, K. Ryu, J.H. Park and S.O. Jung, “A Low-Power and Small-Area All-Digital Delay-Locked Loop with Closed-Loop Duty-Cycle Correction,” International Conference on European Solid-State Circuits Conference, 2012, Page 181-184
|
| 68 |
[Feb. 1-3, 2012]
Y.J. An, K. Ryu, J.H. Park and S.O. Jung, “An All-digital, Voltage and Temperature Independent Process Sensor,” International Conference on Electronics, Information and Communication, 2012, Pages 488-489
|
| 69 |
[Feb. 1-3, 2012]
H.W. Jeong, Y.H. Yang, J.H. Lee, J.S. Kim and S.O. Jung, “SRAM Read Stability and Write Ability Metrics in the Aspect of Accurate Yield Estimation with Supply Voltage Scaling in 22nm FinFET Based SRAM,” International Conference on Electronics, Information and Communication, 2012, Pages 502-503
|
| 70 |
[Nov. 17-18, 2011]
Y.D. Jung, J.S. Kim, K. Ryu, J.P. Kim, S.H. Kang and S.O. Jung, “MTJ based Non-Volatile Flip-flop in Deep Submicron Technology,” International SoC Design conference, 2011, Pages 424-427
|
| 71 |
[May. 2-4, 2011]
Y.H. Yang, J.S. KIM, H.K. Park, J. Wang, G. Yeap, and S.O. Jung, “SRAM Bitcell Design for Low Voltage Operation in Deep Submicron Technologies,” IEEE International Conference on IC Design and Technology, 2011, Pages 1-4 |
| 72 |
[Sep. 19-22, 2010]
H.C. Kang, K. Ryu, D.H. Lee, W. Lee, S.H. Kim, J.R.Choi, and S.O. Jung, “Process Variation Tolerant All-Digital Multiphase DLL for DDR3 Interface,” IEEE Custom Integrated Circuits Conference, 2010, Pages 1-4 |
| 73 |
[May. 2-6, 2010]
H.K. Park, S.C. Song, M.H. Abu-Rahma, L. Ge, M. Kang, B.M. Han, J. Wang, R. Choi, S.O. Jung and G. Yeap, “Accurate Projection of Vccmin by Modeling “Dual Slope” in FinFET based SRAM, and impact of Long Term Reliability on End of Life Vccmin” 2010 IEEE International Reliability Physics Symposium, Pages 1008-1013 |
| 74 |
[Jul. 5-8, 2009]
J.S. Kim, J.H. Song, K. Ryu, S.H. Kang, and S.O. Jung, "A Comparative Study of MRAM Sensing Circuits in 65nm Technology," International Technical Conference on Circuits/Systems, Computers and Communications, Pages 785-788 |
| 75 |
[Dec. 8-10, 2008]
C.H. Park, J.H. Kang, S.O. Jung and I.K Yun "Statistical Modeling of Layout-Dependent Characteristic Fluctuations for Multi-Finger MOSFETs," International Conference on Electron Devices and Solid-State Circuit, Pages 1-4 |
| 76 |
[Jul. 22-24, 2008]
K. Ryu, S.K. Park and S.O. Jung, "A Dual-Edge Triggered Phase Detector for Fast-Lock DLL." The 12th WSEAS International Conference on Circuits, Pages 197-201 |
| 77 |
[Jun. 24-27, 2008]
C.H. Park, J.H. Kang, S.O. Jung and I.K Yun "Variation Analysis of DC Characteristics for Multi-Finger MOSFETs," Proceedings of International Conference on Electronics, Informations and Communications, Pages 327-329 |
| 78 |
[Feb. 2-9 2006]
R. Roy, F. Nemati, K. Young, B. Bateman, R. Chopra, S.O. Jung, C. Show and H. Cho, "Thyristor-Based Volatile Memory in Nano-Scale CMOS," IEEE International Solid-State Circuits Conference, Pages 2612-2621 |
| 79 |
[2006]
M. Elgebaly and S.O. Jung, "PVT-Tolerant Adaptive Voltage Scaling," Qualcomm Technology Forum |
| 80 |
[May. 23-26, 2004]
G. Yang, S.O Jung, S.H. Kim, K.H. Baek and S.M. Kang "A Low-Power 1.85 GHz 32-bit Carry Lookahead Adder Using Dual Path All-N-Logic," IEEE International Symposium on Circuits and Systems, Vol. 2, Pages 781-784 |
| 81 |
[Aug. 4-7, 2002]
G. Yang, S.O Jung, S.H. Kim and S.M. Kang "A Low-Power 2.1 GHz 32-bit Carry Lookahead Adder Using Dual Path> All-N-Logic," IEEE International Midwest Symposium on Circuits and Systems, Vol. 2, Pages 298-301 |
| 82 |
[Jun. 10-14, 2002]
S.O. Jung, K.W. Kim and S.M. Kang "Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages" ACM / IEEE Design Automation Conference, Pages 467-472 |
| 83 |
[Apr. 25-26, 2002]
S.O. Jung, K.W. Kim and S.M. Kang "Optimal Timing for Skew-Tolerant High-Speed Domino Logic" Proceeding of the IEEE Computer Society Annual Symposium on VLSI, Pages 41-46 |
| 84 |
[Mar. 4-8, 2002]
S.O. Jung, K.W. Kim and S.M. Kang "Dual Threshold Voltage Domino Logic Synthesis for High Performance with Delay and Power Constraint" Proceeding of the IEEE Computer Society Design, Automation and Test in Europe Conference and Exhibition, Pages 260-265 |
| 85 |
[May. 6-9, 2001]
K.W. Kim, S.O. Jung and S.M. Kang "Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits," IEEE International Symposium on Circuits and Systems, Vol. 5, Pages 371-374 |
| 86 |
[May. 6-9, 2001]
S.O. Jung, K.W. Kim and S.M. Kang "Noise Constrained Power Optimization for Dual Vt Domino Logic,” IEEE International Symposium on Circuits and Systems, Vol. 4, Pages 158-161 |
| 87 |
[May. 6-9, 2001]
S.O. Jung, S.M. Yoo, K.W. Kim and S.M. Kang "Skew-Tolerant High-Speed(STHS) Domino Logic," IEEE International Symposium on Circuits and Systems, Vol. 4, Pages 154-157
|
| 88 |
[May. 6-9, 2001]
S.M. Yoo, S.O. Jung, and S.M. Kang "Low Cost and High Efficient BIST Scheme with 2-Level LFSR and APTP," IEEE International Symposium on Circuits and Systems, Vol. 4, Pages 1-4
|
| 89 |
[Mar. 16-18, 2001]
S.O. Jung, K.W. Kim and S.M. Kang "Transistor Sizing for Reliable Domino Logic Design in Dual Threshold Voltage Technology," ACM Great Lakes Symposium on VLSI, Pages 133-138
|
| 90 |
[Jun. 18-22, 2001]
K.W. Kim, S.O. Jung, P. Saxena and S.M. Kang "Coupling Delay Optimization by Temporal Decorrelation Dual Threshold Voltage Technique," ACM / IEEE Design Automation Conference, Pages 732-737
|
| 91 |
[Apr. 19-20, 2001]
S.M. Yoo, C. Kim, S.O. Jung, K.H. Baek, S.M. Kang, "New Current Mode Sense Amplifier for High Density DRAM and PIM Architectures,” IEEE International Symposium on Circuits and Systems, Pages 938-941
|
| 92 |
[Apr. 19-20, 2001]
S.M. Yoo, S.O. Jung, and S.M. Kang "2-Level LFSR Scheme with Asynchronous Test Pattern Transfer for Low Cost and High Efficient Built-In-Self-Test," ACM Great Lakes Symposium on VLSI, Pages 93-96
|
| 93 |
[May. 28-31, 2000]
C. Kim, S.O. Jung, K.H. Baek and S.M. Kang "Parallel Dynamic Logic (PDL) and Speed-enhanced Skewed (SSS) CMOS Logic," IEEE International Symposium on Circuits and Systems, Vol. 1, Pages 756-759
|
| 94 |
[Jul. 25-27, 2000]
K.W. Kim, S.O. Jung, Unni Narayanan, C.L.Liu and S.M. Kang "Noise-Aware Power Optimization for On-Chip Interconnect," IEEE International Symposium on Low Power Electronics and Design, Pages 108-113 |
|
