Research goal
- Implementation low-power and high-accuracy spiking neural network SoC
- Development of face-recognition security system platform by using SNN based learning
Description
- Design low-power neuron and synapse model
- Development of mixed STDP learning mechanism
Research goal
- Implementation of high-performance and low-power CNN based SR system on a single chip for real-time up-scaling from FHD to UHD
Description
- Research on computing-in-memory architecture for MAC operations of CNN
- Research on data scheduling and wave-pipelining for chip area reduction
Research goal
- Development of DRAM-PIM architecture with high memory bandwidth optimized for DNN algorithm computing
- Maximize computing throughput and energy efficiency with small area
Description
- Processing-in Memory (PIM) can effectively reduce bandwidth bottlenecks between processors and main memory as demands for higher memory bandwidth increase. This structure uses weight data stored inside the DRAM array to perform DNN operations and then communicate with the processor, enabling efficient use of higher memory bandwidth than existing structures.
- Researching a PIM architectures that is optimized for data-centric applications is expected to facilitate memory market and AI accelerator market expansion
Research goal
- Implementation low-power and area efficient Computing in Memory(CIM) using multi level FeFET
- Neural network accelerator development using FeFET based CIM macro
Description
- Design area efficient multi level FeFET memory array
- Design energy efficient CIM macro for CNN