[2014.8]
Title : VT_Extractor
Designer : Young-Jae An, Kiryong Kim
Process : Samsung 65nm
[2014.1]
Title : Fast Lock DLL for DRAM
Designer : Dong Hun Jung, Young-Jae An
Process : Samsung 65nm
[2008.9]
Title : DLL Based Clock Generator
Designer : Kyung Ho Ryu, Dong Hun Jung
Process : Dongbu 180nm
[2009.8]
Title : DLL for DDR3 PHY interface
Designer : Heechai Kang
Process : Samsung 45nm
[2009.8]
Title : Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector
Designer : Kyung Ho Ryu, Dong-Hoon Jung
Process : Samsung 130nm
[2010.1]
Title : Temperature Sensor2
Designer : SeungHan Woo
Process : Hynix 130nm
[2010.3]
Title : A Low-Power and Small-Area All-Digital Delay-Locked Loop with Closed-Loop Duty-Cycle Correction
Designer : Dong-Hoon Jung, YoungDon Jung
Process : Samsung 130nm
[2010.3]
Title : Temperature Sensor1
Designer : SeungHan Woo
Process : Samsung 130nm
[2010.8]
Title : All-Digital Self-Calibrated Multiphase Clock Generator
Designer : Kyung Ho Ryu, Dong-Hoon Jung
Process : Samsung 130nm
[2011.5]
Title : Retention Flip-Flop
Designer : Heechai Kang
Process : Samsung 130nm
[2011.11]
Title : ASIC chip for next generation high speed ATE
Designer : Kyung Ho Ryu, Dong-Hoon Jung, JungHyun Park, JiWan Jung
Process : Samsung 130nm
[2012.3]
Title : All-digital Process-Variation-Calibrated Timing Generator for ATE with 1.95-ps Resolution and a Maximum 1.2-GHz Test Rate
Designer : Kyung Ho Ryu, Dong-Hoon Jung
Process : Samsung 130nm
[2012.3]
Title : A High Speed, Highly Reliable Frequency Multiplier for a DLL-based Clock Generator
Designer : Kyung Ho Ryu, JiWan Jung, JinHyuk Kim
Process : Samsung 130nm
[2012.4]
Title : All-Digital 90° Phase-Shift DLL with Dithering Jitter Suppression Scheme and Stochastic Analysis of Jitter Characteristic
Designer : Dong-Hoon Jung, JungHyun Park
Process : Samsung 45nm
[2012.8]
Title : Process variation sensor
Designer : Young-Jae An, JinHyuk Kim
Process : Samsung 65nm